1. Field of the Invention
The present invention relates generally to redundant circuit detecting apparatuses, and in particular, to a redundant circuit detecting apparatus for detecting a redundant circuit included in a logic circuit utilizing logic simulation. The present invention has particular applicability to a logic circuit optimization apparatus for optimizing a designed logic circuit.
2. Description of the Background Art
Generally, in designing a semiconductor integrated circuit, a computer aided design system (referred to as "CAD system" hereinafter) is often used. According to the CAD system, a designer designs a logic circuit which fulfills required circuit functions, using a CRT display unit, and then logic simulation is conducted in the designed logic circuit, using test data. When a desired test result is obtained, it is determined that the designed logic circuit fulfills the necessary functions. The fulfillment of the necessary logic functions by the designed logic circuit does not necessarily mean the circuit is optimized. In other words, a redundant circuit often exists in the designed circuit. The presence of the redundant circuit can give rise to the following problems. Area occupied by the logic circuit on a semiconductor substrate increases and, therefore, high density integration of the semiconductor integrated circuit is prevented. Additionally, it is pointed out that complete detection of faults in the designed logic circuit cannot be achieved, because of inability to detect potential faults in the redundant circuit. Generally, the logic circuit cannot operate normally when a fault exists in the logic circuit. The logic circuit does operate normally, however, even when a fault exists in a redundant circuit included in the logic circuit.
As one method of detecting a fault in a redundant circuit included in a designed logic circuit, a method has been conventionally known, which performs fault simulation preparing and using test data other than test data to be used in logic circuit simulation. A large number of operations are however necessary for the preparation, because test data for logic simulation should be prepared for every logic circuit designed in various manners. Furthermore, faults still cannot be detected in the redundant circuit in some cases.
Another method is known, according to which a logic circuit is designed to have a higher fault detecting rate, by utilizing a designing method called Level Sensitive Scan Design (referred to as "LSSD" hereinafter). Referring to FIG. 1, a logic circuit 3 designed according to the LSSD includes three internal circuits 71, 72, 73 and shift registers 81 to 87 connected in series between a serial input 7 and a serial output 8. The shift registers 81 to 87 constitute a scan path. The internal circuit 71 receives parallel input data through a parallel input 9. The internal circuit 73, on the other hand, outputs parallel output data through a parallel output 10. When the logic circuit 3 is designed according to the LSSD, the following restrictions exist. Level sensitive shift registers to respond to a 2-phase clock signal to operate should be used, as the shift registers 81 to 87 constituting the scan path. In addition, desired logic functions should be implemented by a combination of the internal circuits 71, 72 and 73. The restrictions are described in detail in an article by S. DasGupta et al entitled "LSI Chip Design for Testability" (ISSCC DIGEST OF TECHNICAL PAPER, February, 1978, pp. 216-217). In addition to the above mentioned restrictions, it is pointed out that the scale of a circuit is increased by about 20% when the logic circuit is designed according to the LSSD.